I2C core questions (Avalon,... by Tadorta at on Fri Feb 8 17 Hello Thomas, I'm using the i2c_master_top core in my project, and I can tell you that it works properly. The bug exists, is "sda_pad_i <= sda" To use I2C bus you need...
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I2C core questions (Avalon,... by Tadorta at on Fri Feb 8 17 Hello Thomas, I'm using the i2c_master_top core in my project, and I can tell you that it works properly. The bug exists, is "sda_pad_i <= sda" To use I2C bus you need to put external pull up resistors, to force weak high level. To control the i2c_master_top core you need a Wishbone master. I built my own WB. read more... I2C core questions (Avalon,... by Thomas on Thu Feb 7 09 Hello, I'm currently working on connecting the opencores I2C master (VHDL version) to the NIOS 2 processor via the Avalon bus. I intend to run the NIOS 2 on the Altera DE2 board (based on a Cyclone 2 FPGA). So far I've completed the following step: 1) Wrapper code that implements the tri-state buffers. read more... Wbm1_dat_o , is it an input... by Andrewm at on Wed Feb 6 21 Ta guys, I was checking as the wishbone generator has things 'different'. I've reported it as a bug, and I'll do my test bench as per the spec. . read more...
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